It got as far as a breadboarded prototype which worked really well. All the usual stuff like line and load regulation, ripple, noise and dynamic regulation were cool. It even passed the speaker test (connect the loaded output to a small speaker via a capacitor and put it to your ear, you should hear nothing) But then the schematic got lost, and of course the breadboard got plundered for bits. The other day, I found the schematic while looking for a bike inner tube in the basement... how did it get down there... never mind, now I give you THE DOUBLE DRAGON
The cleverness is in U4 (a TL431 adjustable 3-terminal reference) and surrounding circuitry. Biased by the raw DC (via decoupling network R31, R32, C7) it supplies a 12V reference voltage. R15, R16 divide this in two to give you 6V (with an equivalent impedance of 12K) and R3 feeds in a sample of the output. The overall effect is that when the output is 0V, U1B sees about 5V, and when it is 30V, U1B sees 10.8V.
So, the op-amp input doesn't go down to 0V and you don't need a negative rail to make it work. I know you get op-amps whose common-mode range includes ground, but they never seem to work that well at the limit. This way, you can use a fast op-amp and get good dynamic regulation.
The rest is not too bad. U1A provides current limiting, and R11 is the sense resistor. With the values shown, the current limit adjusts from zero to 500mA. To get a different maximum limit, change R11, e.g. for 0-1A it should be 0.5 ohm, and for 0-5A, 0.1 ohm (and a few more pass transistors in parallel)
Firstly, the output capacitor C1 (along with the load resistance) provides the dominant pole. It has to be done this way - otherwise, if you connect a capacitive load, you can get instability. C2 provides a bit of lead. R29 C4 provide a lag, et voila! lead-lag compensation! In case you think I went through the formal lead-lag design procedure, I didn't. I did some spice simulations until I had something that was actually stable, and then tweaked the breadboarded circuit for best dynamic response.
The current limiting loop is compensated too, and for stability's sake it is slower than the voltage feedback loop. So, when the output is shorted, you get a fight between the two feedback loops. For a few hundred microseconds, the voltage feedback wins out and a spike of current gets through. This is the price you pay for good dynamic regulation and a precision current limit. It doesn't seem to do anything any harm.
P.S... If you use a toroidal transformer, the extra inter-winding capacitance will introduce hum (about 20mV peak-peak) on the output when current-limiting. This might not be a problem for you.
